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Two Full Day Certificate Training Course on EDA Tools especially on FPGA Advantage
19/03/2010
Department of Electronics Engineering Offers, 2 full day’s Full time, Certificate Training course on Electronic Design Automation Tools (EDA Tools) especially on “FPGA Advantage: A Software from Mentor Graphics (Asia), Singapore.
Resource Person:
Mr. Salman Zafar (EDA Tools Expert)
RASTEK Technologies Karachi
Registrations Opened till April 2nd 2010
Course Schedule: April 3rd & 4th, 2010
Timings: 10:00 AM to 5.00 PM
Venue: Cyber Interactive Lab, M.UE.T Jamshoro
Organized By
Department of Electronics Engineering, M.U.E.T, Jamshoro in Joint Collaboration with Directorate of Continuing Education, & RASTEK Technologies Karachi
Chief Coordinator:
- Prof. Dr. B.S. Chowdhry
Chairman
Deptt. of Electronic Engineering
Course coordinators:
- Engr. Farida Memon
- Engr. Mehboob Khowaja
- Engr. Attiya Baqai
- Engr. Kamran Kazi
Objective
- This course enables participants to have a clear insight of FPGA Logic Boards that help engineers gain new skills and advance new designs.
- This course offers a real time simulation of EDA tools & their implementation on hard ware.
- This course is designed such that the participants, both potential students and people from engineering design, operation and maintenance will be benefited out of it.
COURSE OUTLINE & DAY WISE BREAKUP
Day 1: BASIC LEARNING
Introduction to FPGA, How to start FPGA Design, Build conceptual HDL designs quickly using HDL Designer Series ,Build HDL state machines, block diagrams, truth tables, and flow charts ,Debug and verify your conceptual design using Modelsim®
DAY 2 : ADVANCE LEVEL
Create test bench designs quickly, Synthesize your HDL design into a wide range of physical FPGAs using Precision RTL, Optimize your design for speed and area , Use hierarchical designs effectively, Perform static timing analysis, Use top-down and bottom-up design techniques, Use pre-defined macro functions, IPs and vendor specific macro generators, Reuse design elements, Perform gate level verification, compare waveforms against RTL simulation
MG Tools Used: (FPGA Advantage)
HDL Design Series, Modelsim for Functional Verification, Precision RTL for synthesis.
Proposed Workshop Fees / Seat Distributions
Classification
|
Allocated Seats
|
Fees (Rs.)
|
MUET IEEE Chapter Students.
|
05
|
1800
|
MUET students/Faculty Members
|
20
|
2000
|
Faculty Members from Other universities.
|
05
|
2500
|
Limited Seats: First Come – First serve Basis
|
For Further Information Contact
- Dr.Khalil-ur Rehman Dayo
(Assistant Professor, Dept: Electronics Engg, M.U.E.T)
Tel: 0333-2751841
PABX: 022-2772250-70 Ext. 4103
Email: [email protected] - Engr. Irfan Ahmed Halepoto
(Assistant Professor, Dept: Electronics Engg, M.U.E.T)
Tel: 0346-2730197
PABX: 022-2772250-70 Ext. 4123
Email: [email protected]